EASY: Benchmark Results for Efficient Arbiter Synthesis from Multi-threaded Code

Jiany Cheng from Imperial College London created a dataset containing measured results for the EASY (Efficient Arbiter SYnthesis) tool. The data likely includes performance and area metrics for hardware synthesized from multi-threaded C/C++ code using the LegUp HLS tool. The results show up to 87% area savings and up to 39% improvement in execution time for a set of typical application benchmarks.

Use Cases

• Benchmarking hardware synthesis tools based on area savings and execution time improvements mentioned in the description.
• Evaluating static analysis techniques for proving memory bank access patterns in multi-threaded code.
• Comparing arbiter simplification methods for FPGA-based hardware designs.
• Validating formal verification approaches using SMT solvers like Boogie for HLS workflows.

Strengths

• Results show concrete performance improvements, including up to 87% area savings and up to 39% execution time improvement.
• The dataset is associated with a peer-reviewed research paper and implementation in the LLVM framework.
• The approach supports arbitrary input code with irregular memory access patterns, as stated in the description.

Limitations

• Column-level documentation is absent; field semantics must be inferred after download.
• Row count is unknown, which may limit suitability assessment.
• Data may reflect bias inherent to the specific application benchmarks selected for the research paper.

Provenance

Source

Jiany Cheng, Imperial College London

Collection Method

Measured results from integrating the EASY analysis tool with the LegUp HLS tool on a set of application benchmarks.