DULLEA: Hardware-in-the-Loop Register Trace for Asymmetric Multiprocessing

A specialized Hardware-in-the-Loop (HIL) register trace and data matrix captured across asymmetric multiprocessing architectures. The dataset benchmarks interactions between fixed-point clamping math and safety monitors under simulated high-voltage inductive surges. It was created by Jamie Davis and last updated on June 2, 2026.

Use Cases

• Benchmarking real-time fixed-point clamping performance based on signed fractional q15_16_t step-response matrices.
• Analyzing inter-core safety monitor interactions based on dual-core temporal register logs tracking bus arbitration delays.
• Validating static memory partition isolation based on the static boundary layout manifest confirming zero dynamic heap use.

Strengths

• Cycle-accurate timing data includes microsecond and clock cycle counts captured via hardware trace units.
• Documents a specific, constant-time execution of 14 cycles on Core 1 and zero cache-invalidation stalls on Core 2.
• Clear industrial application focus for validating fail-secure systems in aerospace and automotive domains.

Limitations

• Description metadata is limited; actual data quality requires manual inspection after download.
• Row count is unknown, which may limit suitability assessment.
• Column-level documentation is absent; field semantics must be inferred after download.

Provenance

Source

Jamie Davis via figshare

Collection Method

Captured via hardware trace units (DWT->CYCCNT) across asymmetric multiprocessing architectures.

Freshness

Last updated 2026-06-02 20:31:39; freshness should be verified.