Davis Logic V2: DULLEA-Mobile SoC Efficiency Profiles for DVFS

A high-fidelity behavioral state map engineered to optimize Dynamic Voltage and Frequency Scaling (DVFS) and task migration across smartphone multi-core SoCs. The dataset is formatted as a packed Q16.16 fixed-point integer matrix for real-time kernel-space scheduling and was generated via Hardware-in-the-Loop (HIL) state simulations targeting Energy-Delay Product (EDP) boundaries. It was authored by Jamie Davis and last updated on June 2, 2026.

Use Cases

• Optimizing Dynamic Voltage and Frequency Scaling (DVFS) policies based on pre-computed multi-objective lookup profiles.
• Implementing deterministic, sub-40ns task migration decisions to replace power-expensive neural network evaluations.
• Proactively minimizing energy using active exponential thermal barrier penalty functions to prevent core throttling.

Strengths

• Dataset is designed for deterministic sub-40ns array distance resolution, enabling real-time use.
• Generated and validated via rigorous Hardware-in-the-Loop (HIL) state simulations.
• Provides proactive energy minimization profiles with a specific thermal penalty function.

Limitations

• The dataset is very small at 2.1 KB, indicating a limited scope or highly compressed representation.
• Column-level documentation is absent; field semantics must be inferred after download.
• Row count is unknown, which may limit suitability assessment.

Provenance

Source

Jamie Davis via figshare

Collection Method

Generated and validated via Hardware-in-the-Loop (HIL) state simulations.

Freshness

Last updated 2026-06-02 21:25:42; freshness should be verified.