Davis Logic V2: Fixed-Point Lead-Lag Phase Shifter Network (Q16.16)

Module 129 details a zero-heap, zero-copy, real-time First-Order Lead-Lag Phase Shifter Network for bare-metal embedded systems. The module provides a recursive single-pole, single-zero filter network for discrete phase adjustments, using 64-bit integer operations and Q16.16 fixed-point format. It was authored by Jamie Davis and published on figshare under a CC BY 4.0 license, with a last update timestamp of 2026-05-31.

Use Cases

• Tuning frequency-response characteristics in sensor feedback matrices based on the described lead-lag network.
• Implementing deterministic, branchless phase adjustments for real-time embedded control systems based on the module's architecture.
• Studying fixed-point arithmetic implementations for recursive filters based on the Q16.16 format and 64-bit intermediate operations.
• Designing systems requiring overflow-safe signal processing based on the described hardware-level clamping rules.

Strengths

• The module uses 0 bytes of heap memory, eliminating dynamic allocation overhead.
• Computations are designed for microsecond-range loop execution speeds, suitable for real-time applications.
• Outputs are protected from overflow by hardware-level clamping between +2147483647 and -2147483648.

Limitations

• The dataset is very small at 3.5 KB, indicating it is likely a code module or documentation rather than a substantial data collection.
• Column-level documentation is absent; the structure and semantics of any contained data must be inferred after download.
• The description is highly technical and focused on implementation, offering limited context on potential application datasets.

Provenance

Source

Jamie Davis (Independent Systems Architect)

Collection Method

Likely a software module or technical specification authored for the Davis Logic V2 project.

Freshness

Last updated 2026-05-31 22:34:33; freshness should be verified.