Davis Logic V2: Real-Time Deadline Monitoring Kernel for Embedded Systems

2.4 KB of source code for a high-reliability timing protection kernel. The DULLEA module is engineered to monitor cycle-accurate execution bounds and intercept timing failures in embedded control systems on 32-bit bare-metal architectures. Author Jamie Davis uploaded the text file to figshare under a CC-BY-4.0 license on June 2, 2026.

Use Cases

• Benchmarking real-time performance based on the described cycle-accurate deadline verification boundaries.
• Developing fault-tolerant systems based on the described dynamic interception of over-deadline execution loops.
• Studying low-level timing predictability based on the described zero-allocation, freestanding C++ implementation.

Strengths

• The 2.4 KB size suggests a focused, minimal codebase suitable for resource-constrained environments.
• The description provides specific architectural details, including the use of hardware counters and assembly-level synchronization barriers.

Limitations

• Row count is unknown, which may limit suitability assessment.
• Column-level documentation is absent; field semantics must be inferred after download.
• The dataset is very small (2.4 KB), indicating limited scope.

Provenance

Source

Jamie Davis via figshare.

Collection Method

Engineered software module; method of data generation within the module is not specified.

Freshness

Last updated 2026-06-02 18:57:19; freshness should be verified.