Fixed-Point First-Order Allpass Fractional Delay Line (Q16.16)

Module 121 from the Davis Logic V2 project provides a zero-heap, real-time fractional delay line for embedded systems. The component implements a single-multiplier recursive allpass filter to achieve sub-sample phase shifts with a flat 0 dB gain response. It was authored by Jamie Davis and released under a CC BY 4.0 license.

Use Cases

• Implementing fine-grained phase matching in audio synthesis based on the described fractional delay architecture.
• Optimizing real-time signal processing loops for embedded hardware based on the single-update-multiplier efficiency profile.
• Developing overflow-safe digital filters based on the described hardware-level clamping rules for output saturation.

Strengths

• Uses zero bytes of heap memory, as stated in the description.
• Implements hardware-level clamping to prevent overflow, with specific bounds (+2147483647 to -2147483648) mentioned.
• Released under the permissive Creative Commons Attribution 4.0 International license.

Limitations

• Column-level documentation is absent; field semantics must be inferred after download.
• Row count is unknown, which may limit suitability assessment.
• The dataset is very small (4.0 KB), suggesting it is likely a code module or documentation rather than a large-scale data corpus.

Provenance

Source

figshare

Collection Method

Likely created as a software component for the Davis Logic V2 architectural project.

Time Range

null

Freshness

Last updated 2026-05 31 21:21:02; freshness should be verified.

Geography

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