MG-Verilog: Multi-grained Dataset for LLM-assisted Hardware Design

MG-Verilog is a multi-grained dataset created to mitigate limitations in existing resources for LLM-assisted hardware design. The dataset was generated by authors Yongan Zhang, Zhongzhi Yu, Yonggan Fu, Cheng Wan, and Yingyan (Celine) Lin for their research paper. It was last updated on the Hugging Face platform on October 10, 2025.

Use Cases

• Training or fine-tuning large language models for Verilog code generation based on the multi-grained structure described.
• Benchmarking LLM performance on hardware design tasks using the proposed dataset framework.
• Researching methods to enhance LLM-assisted hardware design by addressing dataset limitations mentioned in the description.

Strengths

• Dataset is explicitly designed to address limitations in existing datasets for its domain.
• Dataset is open-sourced, as stated in the description.
• Authors and their affiliation (GaTech-EIC) are clearly identified.

Limitations

• Column-level documentation is absent; field semantics must be inferred after download.
• Row count, file formats, and license information are unknown, which may limit suitability assessment.
• The full description is hosted externally, requiring a visit to the dataset page for complete details.

Provenance

Source

GaTech-EIC (Georgia Tech Electronic Intelligent Computing)

Collection Method

Generated for the research paper 'MG-Verilog: Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generation'.

Time Range

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Freshness

Last updated 2025-10-10 20:05:30.

Geography

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