CircuitNet: Open-Source EDA Data for Congestion and IR Drop Prediction

CircuitNet provides labels for congestion prediction, DRC violations, and IR drop analysis within the Electronic Design Automation (EDA) domain. Developed by the CircuitNet team and updated in 2025, it serves as a standardized benchmark for deep learning applications in integrated circuit design.

Use Cases

• Predicting routing congestion using layout features to optimize chip floorplanning
• Detecting potential Design Rule Check (DRC) violations before the final routing stage
• Analyzing IR drop across power delivery networks to ensure circuit reliability

Strengths

• Covers three distinct EDA challenges: congestion, DRC, and IR drop
• Released under the permissive BSD-3-Clause license
• Updated as recently as 2025 to support modern deep learning research

Limitations

• Specific record counts and feature dimensions are not provided in the metadata
• Lack of public sample data prevents immediate assessment of feature granularity

Provenance

Source

CircuitNet Project

Freshness

Last updated in July 2025.